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From gates to a register
Why the ALU needs no memory, how two NOR gates remember a bit, and how a clock turns latches into a register.
Gates that compute, gates that remember
The ALU needs no memory. A gate is combinational: its output depends only on what its inputs are right now, so change an input and the output follows. The adders and the whole ALU inherit that.
Where memory is needed. The registers on either side of the ALU must hold their bits steady while the gates work on them, and keep them until a new value is written. There is no special memory part inside them. A register is made of the same kinds of gates as the ALU, here NOT, AND and NOR, wired in a different way: an output is led back round to become an input, so the circuit can hold itself in a state. That loop is called feedback.
Notation: A·B is AND, ¬A is NOT, and S and R stand for set and reset.
The smallest memory: two NOR gates
Wire two NOR gates so that each one's output is an input of the other, and the pair has two stable states that it holds for as long as the power is on.
Adding a data input and an enable. An inverter and two AND gates in front turn the pair into a D latch: while enable is 1, Q copies D; the moment enable drops to 0, the latch keeps whatever it last saw. Try it: with enable on, set D; turn enable off; now change D and watch Q stay put.
| enable | D | Q |
|---|---|---|
| 0 | × | holds |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
S = D·enable sets the pair and R = ¬D·enable resets it. With enable at 0 neither can fire, and the two NOR gates simply keep holding each other's output in place.
A clock, and four cells in a row
A register is a row of these cells, one per bit, sharing one enable line. In a CPU that enable comes from the clock: a signal that swings between 0 and 1 billions of times a second and paces everything. The instant it rises, called the clock edge, is the one moment when registers may take in a new value; between edges they hold still while the gates settle. Real CPUs use a sharper cell than the latch for this, the edge-triggered D flip-flop: two latches back to back, arranged so that Q changes only at the rising edge and never "sees through" while the clock is high. Four flip-flops with a shared clock and a load line make a 4-bit register, and the 74HC173 in the Bit Lab's build section is exactly that. Set the D bits, then press the clock:
Between clock edges the D inputs can change freely; nothing reaches Q until the next edge. With load off, the edge is ignored. That is how a CPU writes one register and leaves all the others alone: every register sees the same clock, but only the chosen one has its load line raised.
Where this leads
- The D flip-flop tutorial opens up the edge-triggered cell: the master and slave latches inside it, setup and hold time, and clock-to-Q delay, with an interactive visualisation.
- The Bit Lab shows what the registers feed: an 8-bit ALU with its flags, each flag one flip-flop loaded at the same clock edge as the result.
- The companion page From gates to an ALU builds the adder those registers feed, from five gates up.
- The Digital Design course carries on from signals to a complete working computer.